Design of simple voltmeter based on FPGA

2022-06-22
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Simple voltmeter design based on FPGA

the traditional digital voltmeter design usually takes large-scale (application specific integrated circuit) as the core device, supplemented by a small number of medium-scale integrated circuits and display devices. This kind of voltmeter has simple design and high accuracy, but it lacks flexibility due to the use of devices. Its system function is fixed and it is difficult to update and expand. The speed and flexibility of the designed voltmeter, which uses a chip to control the universal a/d converter, is much better than that of the universal digital voltmeter

reference address of this article:

this article uses step-max10m08 core board and step base board V3.0 backplane to complete the simple voltmeter design. We split the design into three functional modules:

adc081s101_ Driver: drive SPI interface ADC chip to realize analog voltage signal acquisition

bin_ to_ BCD: the method of converting binary data into BCD code

segment_ Led: display the voltage data by driving the independent digital tube

top-down hierarchical design

module structure design

1 ADC introduction

a/d converter, or ADC for short, usually refers to an electronic component that converts an analog signal into a digital signal. The usual analog-to-digital converter converts an input voltage signal into an output digital signal. Because the digital signal itself has no practical significance, it only represents a relative size. Therefore, any analog-to-digital converter needs a reference analog quantity as the conversion standard, and the common reference standard is the maximum convertible signal size. The output digital quantity represents the size of the input signal relative to the reference signal

combined model of analog system and digital system

parallel ADC and serial ADC models

both of the above two are 8-bit ADC models, with a resolution of 2 to the power of 8 equal to 256, that is, VREF is divided into 256 parts, the resolvable analog step is VREF/256, and the quantized data is n = 256 * VIN/VREF

the interface between parallel ADC and digital circuit includes one CLK and eight data pins. CLK is the chip clock pin and data is the chip data pin. Each CLK cycle collects 8bit data from the data pin to complete an analog-to-digital conversion. Therefore, the CLK frequency is equal to the sampling rate

the serial ADC (taking adc081s101 as an example) and the digital circuit interface are three wires (CS, CLK, DIN), compatible with the three wire SPI bus. CS is the chip enable pin, CLK is the chip clock pin, and din is the chip data pin. When the ADC chip is enabled, 1bit data is collected from DIN every CLK cycle. However, according to the timing of adc081s101, 16 clks are required to complete a sampling, so the CLK frequency is at least 16 times the sampling rate

2. The ADC module circuit is connected to the ADC module circuit on the step base board V3.0 backplane used in this design. The circuit diagram is as follows:

adc module circuit

is directly connected to the control end of adc081s101 chip. The ADC has six pins, and the three pin Vin is the function multiplexing of VCC and VREF, that is, VIN = VCC = VREF. The front end of the ADC is the operational amplifier circuit lmv721. The operational amplifier module is a voltage following circuit, and then to the front end is a jump pin, which is used to select the source of ADC sampling signal. When the short-circuit cap shortens pins 1 and 2, the ADC collects potentiometer voltage. When the short-circuit cap shortens pins 2 and 3, the ADC adopts RF terminal or P4 pin signal. In this design, we collect the voltage of the rotary encoder, so we need to use a short-circuit cap to short circuit pins 1 and 2

3. ADC module driver design

adc081s101 serial communication sequence is as follows:

note:

1 When SCLK is idle, it is high level, cpol = 1, rising edge (second edge) sampling, CPHA = 1. If the design of the instantiated generic SPI core is completed, the fourth working mode of SPI needs to be adopted

2. CS signal pull down is effective, After 16 months, Obama said on the official blog of the White House: "we are here because the clock completes an ADC conversion and samples. The first three bits of the sampled data are invalid, and the next are db7~db0 (valid data) , followed by invalid data

for the timing sequence of adc081s101, we use Verilog to design a counter. When the counter values are different, we complete different operations to realize an ADC sampling. The program implementation is as follows:

up to this point, we have completed the driver design of the serial ADC chip adc081s101. 35 system clocks are used in the whole sampling cycle. If we use the 12Mhz clock as the system clock of the module, the sampling rate is FS = 12m/35 = 343ksps, ADC dominant frequency fsclk = 12 MHz/2 = 6mhz

adc081s101 main frequency and sampling rate requirements are as follows. According to the requirements, our current main frequency and sampling rate are insufficient, so when using the module, we can use a higher clock (such as 24MHz) to meet the requirements of the chip

note: the clock frequency fsclk, the minimum value is 10MHz, the maximum value is 20MHz, and the sampling rate is 500ksps~1msps

the module interfaces are as follows: CLK and RST_ N is the system clock and reset, ADC_ cs,adc_ CLK and ADC_ Dat is the ADC control pin, ADC_ Data is ADC sampling data, ADC_ Done generates a pulse corresponding to ADC_ Data gets a valid data

4 Clock acquisition

because a higher clock is required for the ADC module, we instantiate the PLL core to obtain a 24MHz clock, and instantiate the PLL module and adc081s101_ Driver module, and connect the output of PLL with adc081s101_ Dr the CLK connection of the iver module

pll module and adc081s101_ The driver module connection program is implemented as follows:

5 The sampling results show that

assuming that the analog input voltage of ADC is 3.3V, in theory, the sampling data ADC_ The data should be 8'hff, and the data finally displayed by the voltmeter on the nixie tube should be 3.3. How can we convert 8'hff into 3.3 data that can be displayed? This is the reverse operation of ADC quantized data

we know that the quantization operation n = 256 * VIN/VREF,

then the reverse operation is VIN = n * VREF/256, where VREF = 3.3V, so VIN = n * 0.0129

so we need to use FPGA to calculate ADC_ Data * 0.0129 results, and then in order to use decimal display, BCD transcode the results, and then display them on the nixie tube

convert ADC sampling data into voltage data according to rules (multiply by 0.0129). Here, we directly multiply by 129. After BCD transcoding, the decimal point of the obtained data can be shifted to the left by 4 digits. The program implementation is as follows:

binary to BCD code program implementation is as follows:

finally, 20 bits of data output is obtained. Every 4 bits represents a BCD code, so there are 5 valid data. Here, we also need to shift the decimal point to the left by 4 digits, The calculated number should be XX volts, one integer digit and four decimal digits. There are only two nixie tubes on the core board. The highest two BCD codes are displayed on the nixie tube at x.x volts. The one decimal point is lit and the fractional decimal point is extinguished. The program implementation is as follows:

the integrated design block diagram is as follows:

rtl design block diagram

this step completes the simple voltmeter design based on FPGA. Download the program to FPGA. The 1 and 2 pins of P3 interface on the step base board V3.0 backplane are short circuited. Rotate the potentiometer at the upper right corner of the backplane to observe the change of the core board digital tube. At the same time, use a multimeter to measure the voltage at the P3 short circuit, and compare the results with those on the digital tube

physical drawing:

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